1. Field of the Invention
The present invention relates generally to integrated circuits and, more specifically, to reducing power usage in dynamic random access memory devices during standby periods.
2. State of the Art
Portable electronic devices require data storage, such as a memory device, for providing large storage capacity and low power consumption. To reduce power consumption and extend available power supplies, such as batteries, the memory device typically operates in a low-power mode when stored data is not being accessed. In the low-power mode, supply voltages within the memory device are typically reduced to lower the power consumption of the components. While the supply voltages are varied to reduce power consumption in the low-power mode, data stored within the memory devices must be retained.
In typical electronic devices, large storage capacities are generally desirable. Accordingly, a dynamic random access memory (DRAM), which has a relatively large storage capacity over other types of memories, is frequently utilized. In a DRAM, the data is “dynamic” because the data stored within the memory cells of the memory device must be periodically recharged or “refreshed” to maintain an adequate charge to signify a specific data bit state. By way of example, a conventional DRAM device includes a plurality of memory cells arranged in rows and columns with each memory cell further including an access transistor and a storage capacitor connected in series between a digital line and a reference voltage generally equivalent to VCC/2.
The data stored in the memory cell in the form of voltage across the capacitor must be periodically refreshed. Generally, once the data is stored in the form of a voltage across the capacitor and the access transistor is deactivated, leakage currents result in this stored voltage which change over time and, if not refreshed, may result in a different binary state of data being stored in the memory cell. Those of ordinary skill in the art appreciate that in a conventional DRAM memory cell, the storage capacitor is recharged each time the memory cell is read as the reading operation refreshes or recharges the memory cell to an adequate voltage level to retain the corresponding logic information stored therein.
It should be appreciated that since the charge stored within the storage capacitor depletes, the refreshing operation must be performed at a specified rate in order to retain the logic stored within the memory cells. The rate at which the data stored in the memory cells must be periodically refreshed is known as the “refresh rate” of the memory cells and is a function of a number of different parameters including the operating temperature of the DRAM, the number of rows of memory cells in the array and the value of the supply voltage VCC applied to the DRAM, to name a few. As the supply voltage VCC decreases, the refresh rate increases due, for example, to a reduced voltage being stored across the storage capacitors and the need to refresh this voltage more frequently to ensure the stored voltage does not decay to an insufficient level due to the leakage currents. The refresh rate also must increase as the supply voltage VCC decreases to minimize the possibility of restoring incorrect data into the memory cell.
Where the memory cell is contained in a DRAM, a memory controller typically reads data from the desired memory cells in response to requests from a microprocessor or other control unit causing each accessed memory cell to be automatically refreshed as described. However, the data stored in all the memory cells must be periodically refreshed and, as a result, a periodic refresh command to the DRAM containing the memory cells must be issued thereby causing the control circuitry to access each memory cell. Even when the memory controller is not accessing the DRAM, the memory cells must still be periodically refreshed. To refresh the memory cells under such conditions, the memory controller issues a self-refresh command to the DRAM placing the DRAM in a self-refresh mode of operation during which circuitry internal to the DRAM periodically refreshes the memory cell.
The issuance of a self-refresh command to a DRAM by a microprocessor, for example, signifies that the microprocessor or other controlling circuitry is preoccupied with other functionality and is not in need of imminent data from the DRAM.
While some progress has been made at reducing power consumed by a DRAM when in various standby-like modes, additional improvements are highly desirable. Therefore, there is a need for an improved approach for further minimizing the power consumed by a DRAM.